1. Technical Field
This invention relates to multilayer dielectric material integrated circuit packaging substrates, and more particularly to such a substrate which is adapted to provide multiple integrated circuit operating voltages at the integrated circuit mounting surface thereof.
2. Background Art
The use of multilayer dielectric (e.g., ceramic) substrates for mounting and interconnecting integrated circuit devices is well known in the art. Multilayer ceramic substrates are fabricated of multiple layers of green ceramic sheets which are metallized stacked, laminated and fired to form a monolithic ceramic package. Once fired, the multilayer ceramic substrate provides a three dimensional packaging structure which includes wiring in what was formerly waste or inaccessable space within the substrate.
The internal structure of the multilayer ceramic substrate includes a plurality of signal planes, each having a predetermined metallization pattern. Vias electrically connect predetermined signal planes to one another, to the integrated circuit mounting surface (hereinafter referred to as top surface) and to the input/output pin surface (hereinafter referred to as bottom surface) of the substrate. Also included are a plurality of power distribution planes and associated vias, for electrically connecting integrated circuit operating voltages supplied at predetermined input/output pins on the bottom surface, to appropriate integrated circuit mounting positions on the top surface.
In the present state of the art, it is common to employ large scale integrated circuit chips which require a plurality of operating voltages. Moreover, it is also common to employ integrated circuits from different manufacturers which may likewise require different operating voltages. The requirement for multiple operating voltages complicates the multilayer ceramic substrate, with a consequent yield and reliability impact, as described more particularly below.
Operating voltage distribution in the multilayer ceramic substrate is typically accomplished by providing a power distribution plane for each operating voltage. One or more vias electrically connect the power distribution plane to an appropriate input/output pin at the bottom surface. An appropriate operating voltage is supplied to each input/output pin from a motherboard or card, or by directly connecting an appropriate power supply to the pin. Vias also electrically connect each power distribution plane to appropriate integrated circuit mounting positions at the top surface, so that the required operating voltages are provided to each integrated circuit chip. Thus, each distinct operating voltage requires an input/output pin and a power distribution plane.
In the state of the art circuit packaging environment described above, up to five or more different operating voltages may be required. Accordingly, up to five or more pins and power distribution planes may be required. Unfortunately as the circuit packaging density increases, it becomes difficult to provide the requisite number of input/output pins. Moreover, each power distribution plane requires a separate internal layer in the multilayer ceramic substrate. It is well known that an increase in the number of internal layers dramatically increases cost and adversely impacts manufacturing yield and reliability. Finally, the requirement of multiple voltages at the input/output pins complicates the motherboard or card and complicates the power supply which supplies the multiple voltages. Accordingly, the requirement for an input/output pin and a power distribution plane for each operating voltage limits the ability to employ multiple voltage integrated circuits or integrated circuits from different manufacturers in multilayer ceramic packaging technology.